Telecommunications timing signal generators (TSGs) commonly incorporate redundant frequency synthesizers such that no single failure will interfere with the generation of the output signal. Because only one of the frequency synthesizers is selected at any particular time, the failure of the selected frequency synthesizer initiates a rearrangement such that a backup frequency synthesizer is selected. In the simplest design, no attempt is made to synchronize the phases of the frequency synthesizers. This results in a rearrangement that generally causes a large phase hit on the output.
One prior art approach compensates for the differential delay between the frequency synthesizers by adding equivalent delays in the output signal path. FIG. 1 illustrates a block diagram of a prior art implementation of the delay-compensation method of frequency synthesizer synchronization. Two independent digital frequency synthesizers, driven by separate local oscillators and tuning inputs, are both made to track the same external reference frequency. To prevent reference rearrangement from causing output phase hits, the frequency synthesizer outputs are compared in phase, producing an error signal which is amplified and integrated by some transfer function A, and then applied to the control input of the variable delay which follows the frequency synthesizer chosen to be the slave.
In practice, the variable delays may need to be of relatively complex design to permit unlimited range of compensation over time. Furthermore, during a slave-to-master transition in a clock rearrangement, the value of the delay applied to the slave frequency synthesizer must be latched and held.
In another prior art approach, the output of the selected frequency synthesizer is used as the tracking reference for the backup frequency synthesizer, using the normal tracking hardware and firmware. However, it requires two alterations to the tracking algorithm in order to be useful: phase alignment to the reference is required, and the tracking bandwidth must be greatly increased in order to maintain phase lock in the presence of output wander.
It would be desirable to have a phase-locked digital frequency synthesizer that did not require integration in the feedback path or explicit storage of delay compensation. It would be further beneficial if the frequency synthesizers had a high bandwidth of synchronization feedback loop without firmware intervention.